This invention relates to a circuit for transmitting synchronously and asynchronously occurring data, of which the synchronously occuring data are transmitted by means of a plesiochronous data transmission system.
A plesionchronous synchronous data transmission system, as is known, is comprised of a send-side multiplexer having two or more inputs and one output, a receive-side multiplexer having one input and two or more outputs, an autonomous send-side clock generator, and an autonomous receive-side clock generator, whose clock frequencies generally differ slightly from one another. The output of the send-side multiplexer and a send-side transmission equipment are connected by a communication link and by a receive-side transmission equipment to the input of the receive-side multiplexer.
By using a known plesiochronously operated synchronous data communication link, synchronously data may be transmitted. Both on the send-side and on the receive-side there are provided autonomous central clock generators, whose clock signal frequencies differ slightly from one another and deviate only a little from a given nominal value. In addition, a send-side multiplexer is operated with send-side clock signal which are derived by means of the send-side central clock generator, and a receive-side multiplexer is operated concurrently therewith. Buffer storages are connected to outputs of the receive-side multiplexer. The data are routed to the buffer storages in synchronism with the clock pulse of the send-side clock signal and transmitted in synchronism with the clock pulse of the receive-side clock signals. This operating mode is called a plesiochronous operation. Accurate data transmission is possible despite the slightly different clock frequencies if the data appearing synchronously at the individual inputs of the send-side multiplexer are routed with blank intervals within a predetermined bit frame, it being assumed that the buffer storage capacities are sufficiently large to compensate for the speed differences between the data on the receive-side. If the capacity of the receive-side buffer storages is insufficient, it may be expected that the send-side bit frame differs from that of the receive-side, thereby producing an occasional "bit slip".
If, in addition to data occuring synchronously, asynchronously occuring data must also be transmitted, it is conceivable, in principle, to transmit with an asynchronous data transmission system both the synchronously and the asynchronously occuring data. Such a system would, however, have the disadvantage that it requires a larger transmission capacity for transmitting synchronously occurring data than when using a plesiochronously operated sychronous data transmission system.
It is possible by means of a plesiochronously operated synchronous data transmission system to transmit to receive-side subscribers the synchronously occurring data and the synchronously occurring data by using a send-side submultiplexer, the send-side multiplexer, the communication link, the receive-side multiplexer, and a receive-side submultiplexer. In the latter case the send-side devices and the send-side submultiplexer are pulsed by means of an autonomous send-side clock generated, and the receive-side devices and the receive-side submultiplexer are pulsed by means of the autonomous receive-side clock generator. Assuming this, the send-side submultiplexer would emit synchronously occurring data, which could be transmitted synchronously to the receive side. However, these synchronously queueing data of the send-side submultiplexer queue without spaces between them, so that rate differences between the data on the send-side and those on the receive-side could not be compensated by the means of a buffer storage. Thus, it must be assumed that a bit slip occurs in the area of the receive-side submultiplexer, which causes failure of the time division mutiplex frame alignment, so that all output channels of the receive-side submultiplexer are momentarily blocked, and a phase readjustment of the system is necessary.
An object of the invention is, therefore, to provide a means for transmitting, by means of a plesiochronously operated synchronous data transmission system, synchronously occurring data and asynchronously occuring data without causing a bit slip.
More particularly, it is an additional object of the invention to transmit under the circumstances specified above synchronously occurring data and code-frame-found data or data through asynchronously occurring bit transitions without the danger of a bit slip.
Code-frame-found data are understood to mean, for example, telegraph signals, each of which consists of a start bit, two or more information bits and one stop bit. It is assumed that the individual signals occur asynchronously at arbitrary times, even if the individual bits of each signal lie in different bit frames. Thus, the data both in the code-frame-found data and in the asynchronously occurring bit transitions are asnchronously occurring data.